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documentation:hardware:m2:devgal

DEV Card GALs disassembly and replacement.

U2104

GAL22V10 .

Signals :

inputs :

GAL pinSignal
233.3 MHz clock
3
4/BR CPU1
5/BR CPU0
6/TS CPU0
7TC1 CPU0
9TC0 CPU0
10TT1 CPU0
11/TBST CPU0

Inputs Pin 12,13,16 are grounded

Outputs:

GAL PinSignal
17/BG CPU1 (or R2124)
18/BG CPU0
24R2122 ??
27delayed 1 … (Reset?)

Signal logic:

/TBST - Transfer burst (active low)

/TS - Transfer start (active low)

/BR - Bus request by CPU (active low)

/BG - Bus grant to CPU (active low)

TC0-TC1 are the transfer code:

[TC0:TC1]ReadWrite
00Data transactionNormal write
01-Copy-back line-fill
10Instruction fetch-
11--

TT0-TT4 are the transfer type of the transaction.

[TT0:TT4] Command Transaction
00000 Clean block Address
00100 Flush block Address
01000 SYNC Address
01100 Kill block (dcbz) Address
10000 EIEIO Address
10100 Write via ecowx Nonburst write
11000 TLB invalidate Address
11100 Riad via eciwx Nonburst read
00001 Resv set via lwarx Address
00101 Resv clear via stwcx Address
01001 TLBSYNC Address
01101 ICBI Address
1xx01 - -
00010 write-with-flush Nonburst write
00110 write-with-kill Burst
01010 Read Nonburst read or burst
01110 read-with-intent-to-modify Burst
10010 write-with-flush-atomic Nonburst write
10110 - -
11010 Read atomic Nonburst read or burst
11110 read-with-intent-to-modify atomic Burst
00×11 - -
01011 read-with-no-intent-to-modify Nonburst read or burst
01111 - -
1xx11 - -

Possible implementation:

module u2104(clk,ntbst,nts,nbr,nbg,tt1,tc,unknownin,unknownout);
input wire clk;
input wire ntbst;
input wire nts;
input wire [1:0]nbr;
output wire [1:0]nbg;
input wire tt1;
input wire [1:0]tc;
input wire unknownin;
output wire unknownout;

reg[1:0] bgout;
assign nbg=unknownin?2'b11:bgout;

wire master_is_busy;

//grant master bus on any request or during the active transaction
//grant slave bus only when requested and master is not busy with anything
//don't grant the bus if bridgit is requesting it

always@(posedge clk)
   bgout<={(!master_is_busy & !br[1] & br[0])?0:1),{(!br0|master_is_busy)?0:1};

reg master_is_writing;
reg master_is_reading;

//master is considered busy if it's reading, writing or in the middle of the burst
assign master_is_busy=master_is_writing | master_is_reading | !ntbst;

//writing is any transaction start with data transfers and data type1 is 0
always @(posedge clk)
   master_is_writing<=(!ts & !tc[0] & !tt1);

//reading is any transaction start with type1 is 1
always @(posedge clk)
   master_is_reading<=(!ts & tt1);

//just delayed 1 for now, didn't see any activity
reg delay;

always @(posedge clk)
    delay<=1'b1;

assign unknownout=delay;

endmodule
documentation/hardware/m2/devgal.txt · Last modified: 2022/10/28 09:09 by fixelsan