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documentation:hardware:opera:arm
Table of Contents
The 3DO uses an ARMv3 based processor: the ARM60.
- 32bit Addressing
- Clocked at 12.5MHz
- 10 MIPS @ 12MHz
Datasheets / Documents
Docs about ARM from 3DO
RAM and Hardware Access Latency
| Non-sequential RAM | 5 ticks |
| Short non-sequential | 3 ticks (add internal if page changed) |
| Sequential RAM reads | 2 ticks |
| Sequential RAM writes | 2 ticks |
| Internal | 2 ticks |
| Non-sequential CLIO registers | 5 ticks minimum |
| Sequential CLIO registers | 3 ticks minimum |
| Non-sequential MADAM registers | 5 ticks minimum |
| Sequential MADAM registers | 2 ticks minimum |
| ROM | 35 ticks |
| Non-sequential Trace | 5 ticks minimum |
| Sequential Trace | 3 ticks minimum |
| SPORT reads | 7 ticks |
| SPORT writes | 6 ticks |
| SlowBus (short) | 7 ticks |
| SlowBus (long) | 13 ticks |
| Hardware after Internal | 5 ticks, but 2nd tick is longer (hw decoder) |
documentation/hardware/opera/arm.txt · Last modified: 2022/10/08 19:10 by trapexit
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