3DO Development Repo

GAL22V10 .

Signals :

inputs :

Inputs Pin 12,13,16 are grounded

Outputs:

/TBST - Transfer burst (active low)

/TS - Transfer start (active low)

/BR - Bus request by CPU (active low)

/BG - Bus grant to CPU (active low)

TC0-TC1 are the transfer code:

TT0-TT4 are the transfer type of the transaction.

module u2104(clk,ntbst,nts,nbr,nbg,tt1,tc,unknownin,unknownout);
input wire clk;
input wire ntbst;
input wire nts;
input wire [1:0]nbr;
output wire [1:0]nbg;
input wire tt1;
input wire [1:0]tc;
input wire unknownin;
output wire unknownout;

reg[1:0] bgout;
assign nbg=unknownin?2'b11:bgout;

wire master_is_busy;

//grant master bus on any request or during the active transaction
//grant slave bus only when requested and master is not busy with anything
//don't grant the bus if bridgit is requesting it

always@(posedge clk)
   bgout<={(!master_is_busy & !br[1] & br[0])?0:1),{(!br0|master_is_busy)?0:1};

reg master_is_writing;
reg master_is_reading;

//master is considered busy if it's reading, writing or in the middle of the burst
assign master_is_busy=master_is_writing | master_is_reading | !ntbst;

//writing is any transaction start with data transfers and data type1 is 0
always @(posedge clk)
   master_is_writing<=(!ts & !tc[0] & !tt1);

//reading is any transaction start with type1 is 1
always @(posedge clk)
   master_is_reading<=(!ts & tt1);

//just delayed 1 for now, didn't see any activity
reg delay;

always @(posedge clk)
    delay<=1'b1;

assign unknownout=delay;

endmodule