• Patent: wo09416383a1_-_digital_signal_processor_architecture.pdf
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• 16bit words
• 20bit ALU
• 20bit accumulator
• 512 words of “N” memory (iNstruction memory)
• 256 words of “I” memory (Internal memory)
• 128 words of “EI” memory (external input memory)
• 16 words of “EO” memory (external output memory)
• 13 DMA input channels (from DRAM), buffered by 8 sample deep FIFO
• 4 DMA output channels (to DRAM)
• 2 modes: one for audio processing (cyclic) and one for general purpose processing (free-running)

From page 27 of the patent:

Instruction words can either be arithmetic or control instructions. if bit 15 is 0, then the instruction is an arithmetic instruction, and if bit 15 is 1, the instruction is a control instruction.

Found in Figure 7 on page 95 of patent WO09416383A1.

Descriptions of fields are in the specific sections found below.

Inputs for conditional branch are the status flags, mode bits, flag select, and flag mask. The patent includes pseudo code for determining if a branch is to be taken. A_C refers to bit 15 of the instruction.

Md0   = (!MODE1 && !MODE0);
Md1   = (!MODE1 &&  MODE0);
Md2   = ( MODE1 && !MODE0);
Md3   = ( MODE1 &&  MODE.0);
Stat0 = ((FLAG_SELECT && C) || (!FLAG_SELECT && N));
Stat1 = ((FLAG_SELECT && Z) || (!FLAG_SELECT && V));
New_Stat0 = (Stat0 != Md2);
New_Stat1 = (Stat1 != Md2);
tmp_dcare0 = (!FLAG_MASK0 || (FLAG_MASK0 && New_Stat1));
tmp_dcare1 = (!FLAG_MASK1 || (FLAG_MASK1 && New_Stat0));
Really_Dcare = (!FLAG_MASK1 && !FLAG_MASK0);
Md12_Success = (tmp_dcare1 && tmp_dcare0 && (MODE1 != MODE0) && !Really_Dcare);
Super_Duper0 = (A_C && Md1 && !FLAG_SELECT && Really_Dcare);
Super_Duper1 = (A_C && Md1 && FLAG_SELECT && Really_Dcare);
All_Zero = (Super_Duper0 && Z && X);
Not_All_Zero = (Super_Duper1 && !(Z && X));
Sd_Success = (All_Zero || Not_All_Zero);
Nvtest = ((((N != V) || (Z && FLAG_MASK0)) != FLAG_MASK1) && !FLAG_SELECT);
Tmp_Cz = (C && !Z);
Cztest = ((Tmp_Cz != FLAG_MASK0) && FLAG_SELECT && FLAG_MASK1);
Xactest = ((X != FLAG_MASK0) && FLAG_SELECT && FLAG_MASK1);
Md3_Success = ((Nvtest || Cztest || Xactest) && Md3);
Branch = ((Md12_Success || Md3_Success || Sd_Success) && A_C);

Branch always to BCH_ADDRESS

Jump to subroutine at BCH_ADDRESS; store current PC in SUBR register.

Branch from a branch target stream to a new BCH_ADDRESS.

Move the following operand to the specified register, director or indirect.

Move the following operand to the specified address, direct or indirect.

or

No operation

Branch to address indicated by accumulator ACC (13:4)

Change Register base value that is specified in 5:0 of instruction.

Change register mapping latch to that specified in 2:0 of instruction.

Return from subroutine to main instruction sequence. PC = SUBR.

Change operand mask bits to those specified in 4:0 of instruction.

Wait until reset by underflow output of counter or external reset signal.

indicate the number of operands which follow the instruction

indicates whether an ACC/carry word or one of the operands is to be used for the second input of the multiplier

indicate which selections should be made by the dual multiplexer in providing operands to the ALU; bits 11:10 (ALU_MUX_A) select the source for 'A' input port of the ALU and bits 9:8 (ALU_MUX_B) select the source for the 'B' in put port of the ALU.

The ALU function.

For all BSELs except 1000, the shift type (arithmetic or logical) is determined by bit 7, which is the same as the high order bit of ASEL. Basically, if the ALU function is arithmetic, so will the shift be arithmetic. If the ALU function is logical, so will the shift be logical. If BSEL = 1000, then an operand is loaded which specifies both the shift type and a new BSEL explicitly. If the newly loaded operand is itself 1000, then the barrel shifter performs a 1-bit left rotate of bits 19:4 with bit 19 being rotated into the carry bit.

The “clip on overflow” function of the barrel shifter essentially prevents the ALU from exceeding the largest positive or negative number which can be represented in 20 bits. In this function, if the overflow (V) output of ALU is set, the barrel shifter will output the largest positive number if the sign bit from the ALU is negative, or the largest negative number if the sign bit from the ALU is positive. Clip on overflow is useful esspecially in digital filter applications.

Justify bit (bit 13) indicates whether the 13bit immediate value is to be left or right justified in the 16bit field. If it is to be left justified, then zeros are added to the right, and if it is to be right justified, then the value is sign extended to the left.

The value used for the instruction in question.