The ARM instruction set has the following key features, some of which are common to many other processors, and some of which are not:

• Load/Store architecture (only load and store instructions access memory).
• 32 bit instructions, 32/8 bit data words/bytes.
• 32 bit addresses (26 bit on earlier ARMs).
• 15 general purpose 32 bit registers, program counter and program status register - a subset of these are banked, to give rapid context switching for interrupt and supervisor modes. (See the appropriate ARM Data Sheet for details of particular processors).
• Flexible store multiple and load multiple instructions allow any set of registers from a single bank to be transferred to/from memory by a single instruction.
• There is no single instruction to move an immediate 32 bit value to a register (in general, a literal value has to be loaded from memory). However, a large set of common 32-bit values can be generated in a single instruction.
• All instructions are executed conditionally on the state of the current program status register. Only data processing operations with the S bit set change the state of the current program status register.
• The second argument to all data-processing and single data-transfer operations can be shifted in quite a general way before the operation is performed. This supports, but is not limited to, scaled addressing, multiplication by a small constant, and construction of constants, within a single instruction.
• Co-processor instructions support a general way to extend the ARM's architecture in a customer-specific manner.

In addition, the ARM processor has:

• Support for Big- or Little-Endian memory.
• A powerful barrel shifter to support ARM's within-instruction shifts.

The recipes in this chapter discuss some of these features in greater detail.

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