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documentation:hardware:m2:devgal [2022/11/07 14:49] – created fixelsan | documentation:hardware:m2:devgal [Unknown date] (current) – external edit (Unknown date) 127.0.0.1 | ||
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+ | DEV Card GALs disassembly and replacement. | ||
+ | |||
+ | ==== U2104 ==== | ||
+ | |||
+ | GAL22V10 . | ||
+ | |||
+ | Signals : | ||
+ | |||
+ | inputs : | ||
+ | |||
+ | ^GAL pin^Signal| | ||
+ | |2|33.3 MHz clock| | ||
+ | |3| | | ||
+ | |4|/BR CPU1| | ||
+ | |5|/BR CPU0| | ||
+ | |6|/TS CPU0| | ||
+ | |7|TC1 CPU0| | ||
+ | |9|TC0 CPU0| | ||
+ | |10|TT1 CPU0| | ||
+ | |11|/TBST CPU0| | ||
+ | |||
+ | Inputs Pin 12,13,16 are grounded | ||
+ | |||
+ | Outputs: | ||
+ | |||
+ | ^GAL Pin^Signal| | ||
+ | |17|/BG CPU1 (or R2124)| | ||
+ | |18|/BG CPU0| | ||
+ | |24|R2122 ??| | ||
+ | |27|delayed 1 … (Reset?)| | ||
+ | |||
+ | === Signal logic: === | ||
+ | |||
+ | /TBST - Transfer burst (active low) | ||
+ | |||
+ | /TS - Transfer start (active low) | ||
+ | |||
+ | /BR - Bus request by CPU (active low) | ||
+ | |||
+ | /BG - Bus grant to CPU (active low) | ||
+ | |||
+ | TC0-TC1 are the transfer code: | ||
+ | |||
+ | ^[TC0: | ||
+ | |00|Data transaction|Normal write| | ||
+ | |01|-|Copy-back line-fill| | ||
+ | |10|Instruction fetch|-| | ||
+ | |11|-|-| | ||
+ | |||
+ | TT0-TT4 are the transfer type of the transaction. | ||
+ | |||
+ | ^[TT0: | ||
+ | |00000 | ||
+ | |00100 | ||
+ | |01000 | ||
+ | |01100 | ||
+ | |10000 | ||
+ | |10100 | ||
+ | |11000 | ||
+ | |11100 | ||
+ | |00001 | ||
+ | |00101 | ||
+ | |01001 | ||
+ | |01101 | ||
+ | |1xx01 | ||
+ | |00010 | ||
+ | |00110 | ||
+ | |01010 | ||
+ | |01110 | ||
+ | |10010 | ||
+ | |10110 | ||
+ | |11010 | ||
+ | |11110 | ||
+ | |00×11 | ||
+ | |01011 | ||
+ | |01111 | ||
+ | |1xx11 | ||
+ | |||
+ | === Possible implementation: | ||
+ | < | ||
+ | |||
+ | module u2104(clk, | ||
+ | input wire clk; | ||
+ | input wire ntbst; | ||
+ | input wire nts; | ||
+ | input wire [1:0]nbr; | ||
+ | output wire [1:0]nbg; | ||
+ | input wire tt1; | ||
+ | input wire [1:0]tc; | ||
+ | input wire unknownin; | ||
+ | output wire unknownout; | ||
+ | |||
+ | reg[1:0] bgout; | ||
+ | assign nbg=unknownin? | ||
+ | |||
+ | wire master_is_busy; | ||
+ | |||
+ | //grant master bus on any request or during the active transaction | ||
+ | //grant slave bus only when requested and master is not busy with anything | ||
+ | // | ||
+ | |||
+ | always@(posedge clk) | ||
+ | | ||
+ | |||
+ | reg master_is_writing; | ||
+ | reg master_is_reading; | ||
+ | |||
+ | //master is considered busy if it's reading, writing or in the middle of the burst | ||
+ | assign master_is_busy=master_is_writing | master_is_reading | !ntbst; | ||
+ | |||
+ | //writing is any transaction start with data transfers and data type1 is 0 | ||
+ | always @(posedge clk) | ||
+ | | ||
+ | |||
+ | //reading is any transaction start with type1 is 1 | ||
+ | always @(posedge clk) | ||
+ | | ||
+ | |||
+ | //just delayed 1 for now, didn't see any activity | ||
+ | reg delay; | ||
+ | |||
+ | always @(posedge clk) | ||
+ | delay< | ||
+ | |||
+ | assign unknownout=delay; | ||
+ | |||
+ | endmodule | ||
+ | |||
+ | </ | ||
+ | |||
+ | |||
+ | |||